The present invention relates to Electrically Erasable and Progranimable non-volatile semiconductor memory devices, shortly referred to as EEPROMs. More specifically, the invention concerns a new structure of a byte-switch for EEPROMs, having a more compact layout and therefore allowing for a save in semiconductor area.
As known, EEPROMs are arranged per bytes or per words. This arrangement makes it possible to modify the memory content on a per-byte or, respectively, per-word basis, a feature that makes EEPROMs particularly useful in some applications if compared to, e.g., Flash EEPROMs.
This feature is achieved because the control gate of each single memory byte or word is physically distinct from those of the other memory bytes or words, and can be individually addressed in writing, erasing and reading.
FIG. 1 shows a circuit diagram of a portion of a conventional EEPROM memory cell array. The portion depicted in FIG. 1 comprises four memory bytes. Each byte is-connected to a respective control gate line CGL, made of aluminum. Each memory cell of the byte comprises a floating-gate tunnel-oxide MOS transistor 1 in series to a select MOS transistor 2. The drain electrode of the select transistor 2 is connected to a respective bit line BL0-BL7, made of aluminum. The gate electrodes of the select transistors 2 of all the memory cells of a same byte are connected to a same word line WL, made of polysilicon. The source electrodes of the floating-gate transistors 1 of all the memory cells of a same byte are connected together. The control gate electrodes of the floating-gate transistors 1 of all the memory cells of a same byte are connected to a common byte control gate CG of polysilicon and the latter, through a respective byte-switch 3, is in turn connected to the respective control gate line CGL. The byte-switch 3 comprises a MOS transistor having a drain electrode connected to the control gate line CGL, a gate electrode connected to the word line WL, and a source electrode electrically coupled to the byte control gate CG.
Conventionally, selection circuits for selecting the word lines WL, the control gate lines CGL and the bit lines BL0-BL7 are provided externally to the memory cell array.
Selection of a memory byte is achieved by biasing the respective control gate line CGL, biasing the respective word line WL, and biasing the respective bit lines BL0-BL7. In this way, through the byte-switch 3, the voltage on the control gate line CGL is transferred to the byte control gate CG and thus to the control gate electrodes of the floating-gate transistors 1. The voltage put on the word line WL activates the select transistors 2. Consequently, the drain electrodes of the floating-gate transistors 1 are connected to the respective bit lines BL0-BL7. The other bytes connected to the same control gate line CGL are not affected, since they are connected to a different word line WL. The other bytes connected to the same word line WL are not affected, since they are connected to a different control gate line CGL. Thus, only one byte is effectively addressed.
FIG. 2 shows the layout of the detail 4 in FIG. 1, i.e. the byte-switches of four memory bytes. As visible, the structure is symmetrical with respect to both the vertical axis and the horizontal axis. The aluminum control gate lines CGL have lateral extensions 7 which, through contact openings in a dielectric layer 8 (FIGS. 3 and 4), contact an underlying N type diffusion 9 forming the drain electrode of the byte-switch MOS transistor. Electrical connection between the source electrode N type diffusion 5 of the byte-switch MOS transistor 3 and the respective polysilicon byte control gate CG is achieved by means of an aluminum jumper 6 which, through contact openings in the dielectric layer 8, contacts the source electrode diffusion 5 and the polysilicon byte control gate CG, short-circuiting them. The byte control gate CG is formed out of an upper polysilicon level, a lower polysilicon level 11 being used for forming the floating gates of the floating-gate transistors 1. Conventionally, thick field oxide areas 12 separates the active areas of the chip.
Since both the control gate lines CGL and the jumpers 6 are formed out of a same aluminum layer, the distance between them must be sufficient for preventing shorts between the control gate lines CGL and the jumpers 6. It is for this reason that the control gate lines CGL have lateral extensions 7.
It appears clearly that the provision of the byte-switches determines an overhead in the area dedicated to the memory cell array. However, such an overhead cannot be prevented, if the feature of byte or word individual selection is to be maintained. Another fact to be considered is that each byte-switch must to be located adjacent to the respective byte, in other words, the byte-switches cannot be located externally to the memory cell array.
FIGS. 2 to 4 show the situation in the case a manufacturing process is used providing for only one metal interconnection level. However, the situation in terms of area does not change even if a process providing for two metal interconnection layers is used. In fact, one of the two metal layers is normally used to shunt the polysilicon word lines WL so as to reduce the resistivity thereof. Additionally, even if more compact contact arrangements were used (e.g., stacked contacts and vias), which however introduce critical steps in the manufacturing process, the area occupied by the byte-switches is not significantly reduced. Several of the well known processing steps have been omitted for brevity. Examples of most of the omitted steps can be found in Silicon Processing for the VLSI Era, Volume 1: Process Technology, Stanley Wolf and Richard Tauber, Lattice Press, 1986; and Silicon Processing for the VLSI Era, Volume 2; Process Integration, Stanley Wolf, Lattice Press, 1990, both of which are hereby incorporated by reference.
In view of the state-of art described, it is an advantage of the present invention to provide a new structure for a byte-switch suitable for reducing as far as possible the unavoidable overhead of silicon area.
According to embodiments of the present invention, such an advantage is achieved by a byte-switch structure for electrically erasable and programmable non-volatile memories, including a MOS transistor having a drain electrode coupled to a respective metal control gate line, a source electrode coupled to a respective polysilicon byte control gate line which is connected to control gate electrodes of all the memory cells of a same memory byte or word and is formed in an upper polysilicon layer, and a gate electrode coupled to a respective word line. The said source and drain electrodes of the MOS transistor are, respectively, first and second doped regions of a first conductivity type formed in a semiconductor layer of a second conductivity type at opposite sides of said respective word line. These first and second doped regions are formed under the respective metal control gate line. Additionally, the polysilicon byte control gate line insulatively extends under the metal control gate line to overlap the first doped region, and contacts the first doped region through a respective contact opening in an underlying stack formed by an interpoly dielectric layer, a lower polysilicon layer and an oxide layer.
The proposed byte-switch structure allows for a significant reduction of the chip area overhead. A byte-switch according to embodiments of the invention occupies an area which is approximately a half that occupied by a conventional byte-switch.